Not Applicable
Not Applicable
1. Technical Field
This invention relates to analog-to-digital conversion, and more particularly to automatically determining an optimal sampling clock frequency for performing analog-to-digital conversion of a video signal.
2. Background of the Invention
Presentations using multimedia projection display systems have become popular for conducting sales demonstrations, business meetings, and classroom instruction. In a common mode of operation, multimedia projection display systems receive analog video signals from a personal computer (xe2x80x9cPCxe2x80x9d). The video signals represent still, partial-, or full-motion, display images of the type rendered by the PC. The analog video signals are converted into digital video signals to control digitally-driven display devices, such as a transmissive or reflective liquid crystal displays or digital micro-mirror devices (hereafter xe2x80x9clight valvesxe2x80x9d), to form the display images for projection onto a display screen. A wide variety of such display systems are available from In Focus Systems, Inc., the assignee of this application.
A necessary feature of multimedia display systems is compatibility with the various analog video signal modes generated by PCs and other video sources. These modes typically range from 640xc3x97480 to 1600xc3x971200 resolutions provided at image refresh rates ranging from 60 Hz to 100 Hz. The resolution expresses the number of controllable horizontal and vertical pixel elements that can be turned on and off. Given the variety of display modes, multimedia display systems include an interface that converts analog video signals of various modes to digital video signals capable of controlling the light valves.
Analog video signals typically include image information for each of the red, green and blue colors, and timing signals, which may include a horizontal synchronizing pulse (xe2x80x9cHSYNCxe2x80x9d) and a vertical synchronizing pulse (xe2x80x9cVSYNCxe2x80x9d), or a composite image and sync signal. The color image information is stored in the PC memory as digital color data and is converted to the analog video signals by digital-to-analog converters. When composite sync is employed, a conventional sync separator is used to extract the HSYNC and VSYNC timing pulses.
The timing signals synchronize the scanning of the analog video signals across a raster-scanned display device. The HSYNC pulse controls the horizontal scanning timing, and the VSYNC pulse controls the vertical scanning or video frame refresh timing.
FIG. 1 shows that each video frame 1 typically includes a central active video region 2 surrounded by an inactive or blanked margin 3. The resolution of a raster-scanned display refers to the number of displayable image information points (xe2x80x9cpixelsxe2x80x9d) in active video region 2.
Because the light valves employed by multimedia display systems require digital video signals, either the light valve or the display system normally includes an analog-to-digital converter (xe2x80x9cADCxe2x80x9d) for converting the PC-generated analog video signals into a digital format suitable for driving the light valve. The ADC is typically digitizes samples of the analog video signal under control of a voltage-controlled oscillator (xe2x80x9cVCOxe2x80x9d), which is in turn controlled by a phase-locked loop (xe2x80x9cPLLxe2x80x9d) that locks to a predetermined multiple xe2x80x9cnxe2x80x9d of the HSYNC pulses.
FIG. 2 shows an exemplary analog signal waveform 4, with plateau regions (pixel data components) 5 that correspond to the color levels of individual pixels in the image display. Consecutive pixel data components 5 are connected by signal transition regions 6.
FIG. 2 further shows a typical pixel clock waveform 7, which is generated by the VCO. The number n of pixel clock pulses 8 per HSYNC pulse is typically set to match the resolution mode established by the PC or other analog video source. To determine the resolution mode, certain characteristics of the analog video signal, such as the number of HSYNC pulses per VSYNC pulse, may be used to refer to a mode lookup table. The resulting number n is set to equal the number of pixel data components in each horizontal line of the analog video signal, including those in active video data region 2 and blanked margin regions 3 (FIG. 1). For example, for a 640xc3x97480 screen resolution, n may be set to about 800 to include pixels in blanked regions 3 on either side of the 640 pixel-wide active video region 2. Thus, pixel clock pulses 8 would cause the ADC to sample analog signal waveform 4 about 800 times along each horizontal scan line of video frame 1.
FIG. 2 also shows the desired timing relationship between analog signal waveform 4 and pixel clock waveform 7. The number n of pixel clock pulses 8 is set to establish a one-to-one relationship between pixel clock pulses 8 and pixel data components 5 of analog signal waveform 4. This one-to-one relationship requires that the pixel clock signal frequency be equal to the analog video signal frequency. Under this relationship, each pixel data component 5 is sampled by a single pixel clock pulse 8, such that the ADC properly digitizes instantaneous voltage value of each pixel data component 5. Because pixel clock pulses 8 have xe2x80x9cjitterxe2x80x9d zones 9 at their leading and trailing edges, pixel clock pulses 8 should be centered on pixel data components 5, so that the ADC sampling is not randomly shifted by jitter zones 9 into signal transition regions 6 of analog signal waveform 4.
The stream of digitized signal values from the ADC form the digital video data signal that is conveyed to the light valve to activate or deactivate its pixels in a pattern corresponding to the image defined by analog signal waveform 4. Unfortunately, such ADC conversion is often imperfect because of sample timing errors caused by pixel clock pulses 8. Such sample timing errors are typically caused by pixel clock frequency deviations (xe2x80x9ctrackingxe2x80x9d errors) and xe2x80x9cphasexe2x80x9d errors, both of which may degrade the quality of images generated by the light valve or valves.
FIG. 3 shows a typical tracking error resulting from improperly setting the number n of pixel clocks along the entirety of pixel clock waveform 7xe2x80x2. As described above, the number n of pixel clock pulses 8xe2x80x2 should be equal to the number of pixel data components 5 of each horizontal line of analog signal waveform 4. The improper setting of n results in pixel data components 5 being sampled at inconsistent points. For example, n is set too large in pixel clock waveform 7xe2x80x2 (i.e. the frequency is too high). The resultant crowding of the pixel clock pulses 8xe2x80x2 causes an additive leftward drift of pixel clock pulses 8xe2x80x2 relative to pixel data components 5. Such drift causes sampling in signal transition regions 6 as shown by positional bracket A in which leading edges 9xe2x80x2 of the third through sixth of pixel clock pulses 8xe2x80x2 sample in transition regions 6 of analog signal waveform 4. Accordingly, the transition region data will be erroneous and the image information from adjacent non-sampled pixel data components 5 will be missing from the digitized video signal. If n is erroneously set large enough, pixel clock pulses 8xe2x80x2 may be so crowded that individual analog pixel data components 5 may be double-sampled. On the other hand, if n is set too small (i.e. the frequency is too low), the resulting dispersion of pixel clock pulses 8xe2x80x2 results in a rightward drift in which sampling may also occur in signal transition regions 6.
To minimize tracking and phase errors, prior workers have provided some multimedia projection systems with manual controls that permit an operator to adjust the number n and the phase of pixel clocks pulses 8. The controls are adjusted until the projected image appears satisfactory to the eye of the operator. While manual controls are usually effective in achieving an acceptable image quality, adjusting such manual controls is time-consuming and inhibits the user-friendliness of the multimedia projection system.
Accordingly, other prior workers have developed automated pixel clock adjusting techniques. For example, U.S. Pat. No. 5,657,089 for VIDEO SIGNAL PROCESSING DEVICE FOR SAMPLING TV SIGNALS TO PRODUCE DIGITAL DATA WITH INTERVAL CONTROL describes an active video interval detector that generates data indicative of a difference between the detected active video interval and a required reference video interval. A video signal supply interval controller receives the difference data and provides frequency-dividing ratio control data to a programmable frequency divider that is part of the PLL controlling the pixel clock frequency. Over a number of video frames, the difference data is iterated toward zero to achieve accurate pixel clock tracking. Unfortunately, some PCs generate video signals with an indefinite xe2x80x9cblackxe2x80x9d video level, which makes the active video interval difficult to determine. Moreover, the iterative nature of this technique often requires an unduly long time to achieve accurate pixel clock tracking.
Another example of automated pixel clock adjusting techniques is described in U.S. Pat. No. 5,805,233 for METHOD AND APPARATUS FOR AUTOMATIC PIXEL CLOCK PHASE AND FREQUENCY CORRECTION IN ANALOG TO DIGITAL VIDEO SIGNAL CONVERSION, which is assigned to the assignee of this application and incorporated herein by reference. This patent describes employing a mode lookup table to determine an expected number n of pixel clock pulses per scan line and comparing the actual number n with the expected number to generate a tracking error approximation. The number n is adjusted each vertical cycle to iterate toward an acceptable pixel clock frequency. This technique typically requires 16 to 60 video frames to adjust the pixel clock frequency, and there is no certainty that the resulting frequency will result in accurate tracking.
What is needed, therefore, is a fast and accurate technique for generating a pixel clock that is free of tracking errors.
An object of this invention is, therefore, to provide an apparatus and a method for generating an accurate pixel sampling clock for digitizing an analog video signal at optimal pixel locations along the analog video signal.
Another object of this invention is to generate the pixel sampling clock in one vertical period of the analog video signal.
A further object of this invention is to eliminate the need for a prior art mode table that stores approximate starting points for estimating the pixel sampling clock frequency.
A line parameter detection circuit of this invention includes an active video detector that generates an xe2x80x9cactive videoxe2x80x9d signal indicative of a video signal containing video data that exceeds a predetermined threshold level. The line parameter detection circuit further includes three counters that are incremented by a reference clock. The counters are reset and start counting reference clock pulses upon receiving an HSYNC pulse. A left edge register stores the count accumulated in the first counter upon receiving a rising edge of the active video signal, a right edge register stores the count accumulated in the second counter upon receiving a falling edge of the active video signal, and a line length register stores the count accumulated in the third counter upon receiving the next subsequent HSYNC pulse.
Each video signal scan line includes blanking periods between the HSYNC pulses and the active video region. The precise locations and timings of the blanking periods are typically unknown, however the period of the active video region is known because it coincides with the active video signal generated by the active video detector. The timing ratio of the active video region to the blanking periods is determined from the line parameter detection circuit, from which the ratio of total blanking time to total line time is determined. The ratio of total blanking time to total line time is used to calculate the overall tracking period, and from that a tracking number n and pixel clock pulse frequency can be determined.
In particular, a left edge count is stored in the left edge register at the first point in time that the active video signal is asserted. The left edge count is sensed by a microcontroller for each video data scan line in a video frame, and only the smallest of the left edge counts is saved for processing by the microcontroller.
Likewise, a right edge count is stored in the right edge register at the last point in time that the active video signal is asserted. The right edge count is sensed by the microcontroller for each video data scan line in the video frame, and only the largest of the right edge counts is saved for processing by the microcontroller.
A total line count is stored in the line length register and is periodically sensed by the microcontroller for processing.
The microcontroller computes an active clock count by subtracting the left edge count from the right edge count.
Then the microcontroller computes an active region percentage by dividing the active clock count by the total line count.
The microcontroller next computes a tracking number n by dividing a deduced horizontal resolution by the active region percentage. The deduced horizontal resolution, if unknown, is determined by counting the number of HSYNC pulses in the video frame to determine a vertical resolution count and then finding the deduced horizontal resolution from a standard display resolution table.
The microcontroller may optionally compute a pixel frequency by multiplying the reference clock frequency by the tracking number n and dividing the result by the total line count.
This invention allows the tracking number n to be determined without a mode table and within one frame period, whereas prior methods had taken 16 to 60 frame periods to converge on the proper tracking number n.
Additional objects and advantages of this invention will be apparent from the following detailed description of a preferred embodiment thereof that proceeds with reference to the accompanying drawings.